Simulated Annealing-Based Channel Routing on Hypercube Computers

Many times, routing of signal nets in the layout design of VLSI circuits turns out to be a bottleneck in designing complex chips, due to the inherent compute-intensive nature of this task. Parallel processing of the routing problem holds promise for mitigating this situation. In this context, we present a parallel channel routing algorithm that is targetted to run on loosely coupled computers like hypercubes. The proposed parallel algorithm employs simulated annealing technique for achieving near-optimum solutions. For efficient execution, attempts have been made to reduce the communication overheads by restricting broadcast of updates only to cases of interprocessor net transfers. Performance evaluation studies on the algorithm show promising results.